As semiconductor large-scale integrated (LSI) circuit devices are scaled up and accordingly more time is required for implementing LSI circuit device designs, computerized chip layout processes are used more frequently to reduce errors that have been involved in manual layout design procedures. Efforts are being thus directed at developing faster and error-free layout topologies commensurate with the potential capabilities of the computer-aided design (CAD) tools and procedures used for the automated chip layout processes. Typical of such layout topologies are those widely used for transistor gate arrays with regular device arrangements.
An LSI circuit chip with such a regular device distribution feature has rows of logic cells arranged to form logic-building or function blocks and fixed channel areas provided between the rows of logic cells. Over these fixed channel areas are to be formed inter-block wiring areas used principally for the routing of the interconnects between the individual function blocks while inter-cell wiring areas are to be formed over the function blocks implemented by the logic cells principally for the routing of the interconnects between the individual logic cells forming the function blocks.
In such an LSI circuit chip, the spaces required for the inter-cell wiring areas provided for the interconnection of the logic cells vary depending on the logic functions of the function blocks respectively associated with the wiring areas. Furthermore, the function blocks having approximately equal inter-cell wiring areas are distributed randomly in directions in which the function blocks are arranged in rows. By reason of such random distribution of the function blocks, there are irregularities in the width of the inter-cell wiring areas so that each of the inter-block wiring areas defined between such inter-cell wiring areas have locally broadened and narrowed portions. A problem thus arises in that the required spacings between the adjacent rows of logic cells are dictated by the widths which are allowed allocated to the narrowed portions of the inter-block wiring areas. On the other hand, the broadened portions of the inter-block wiring areas bring about a problem that the inter-block wiring areas could not be exploited effectively throughout the widths of the broadened portions. These problems lead to the requirement for an enlarged chip size and accordingly give rise to an increase in the production cost of the chip implementing the gate array.
It is, therefore, an important object of the present invention to provide an improved semiconductor LSI circuit device which will make it possible to utilize the overall real estate available for the LSI circuit device.